Memory BIST (built-in self-test) is an important tool for testing memories (including finding/diagnosing and repairing defects within those memories). As more memory is integrated into chips, thorough BIST test and repair is a requirement in order to ensure reasonable product quality/reliability levels. To improve BIST quality oftentimes more test patterns are run as part of manufacturing test. Total test time can take many millions of cycles when all necessary test patterns are included.
Memory BIST is designed to operate as many memories as possible simultaneously, while still avoiding false failures due to over test. False failures may be due to exceeding the power specification for a certain chip design, amongst other fail modes. For a given chip design, this might be a small subset, whereas for other chip designs this could include virtually all memories. In addition, memory BIST should be able to test with some margin compared to the normal functional application in order to produce good SPQL (shipped product quality level) while minimizing impacts to yield. Also, high quality memory test and repair via extremely thorough test needs to be balanced against test time. Test time can be a major cost component of chips (sometimes reaching into the multi-minute range).
During manufacturing test, the BIST engine executes multiple test patterns to test the connected memories. If a fail is detected during the execution of a pattern, the fail information is collected by the BIST engine. If more fails are detected in any of the subsequent patterns, the new fail information is accumulated with the old fail information in the BIST engine. At the end of the test, the BIST has the information whether any of the memories associated with it has failed. But, it is not possible in such methodologies to know the distribution of fails on a per-pattern basis.